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UP9301 1 UP9301-ds-f0001, may 2015 www.upi-semi.com 5v/12v synchronous-rectified buck controller with reference input the UP9301 is a compact synchronous-rectified buck controller specifically designed to operate from 5v or 12v supply voltage and to deliver high quality output voltage as low as 0.55v. the UP9301 operates at fixed 200/300khz frequency and provides an optimal level of integration to reduce size and cost of the power supply. the UP9301 supports both tracking mode and stand-alone mode operation. the output voltage is tightly regulated to the external reference voltage from 0.55v to 3.0v at tracking mode or to internal 0.6v reference at stand-alone mode. this controller integrates internal mosfet drivers that support 12v+12v bootstrapped voltage for high efficiency power conversion. the bootstrap diode is built-in to simplify the circuit design and minimize external part count. other features include internal softstart, under voltage protection, over current protection and shutdown function. with aforementioned functions, this part provides customers a compact, high efficiency, well-protected and cost-effective solutions. this part is available in (p)sop - 8l packages. !! !! ! operate from 5v or 12v supply voltage "" "" " 3.3v to 12v v in input range "" "" " 0.6 v ref with 1.5% accuracy "" "" " output range from v ref to 80% of v in !! !! ! support tracking mode and stand alone mode operation !! !! ! simple single-loop control design "" "" " voltage-mode pwm control "" "" " fast transient response !! !! ! high-bandwidth error amplifier "" "" " 0% to 80% duty cycle !! !! ! lossless, programmable over current protection "" "" " uses lower mosfet r ds(on) !! !! ! 200/300khz fixed frequency oscillator !! !! ! internal soft start !! !! ! integrated bootstrap diode !! !! ! rohs compliant and halogen free rebmunredr oe gakca pg nikram po tk ramer 8usp1039pu l8-posp p1039p up coraenil/zhk002 8usq1039p uq 1039p uv m573 @ pco dexif/zhk002 8usr1039p ur 1039p uv m522 @ pco dexif/zhk002 8uss1039p us 1039p up coraenil/zhk003 8ust1039p ut 1039p uv m573 @ pco dexif/zhk003 8usu1039p uu 1039p uv m522 @ pco dexif/zhk003 8asv1039pu l8-pos v1039p uv m051 @ pco dexif/zhk003 8asw1039p uw 1039p uv m522 @ pco dexif/zhk003 !! !! ! power supplies for microprocessors or subsystempower supplies !! !! ! cable modems, set top boxes, and xdsl modems !! !! ! industrial power supplies; general purposesupplies !! !! ! 5v or 12v input dc-dc regulators !! !! ! low voltage distributed power supplies general description applications features note: upi products are compatible with the current ipc/jedec j-std-020 requirements. they are halogen-free, rohs compliant and 100% matte tin (sn) plating that are suitable for use in snpb or pb-free soldering processes. ordering information
UP9301 2 UP9301-ds-f0001, may 2015 www.upi-semi.com typical application circuit pin configuration phase boot refin fb vcc ugate ocs lgate 12 3 45 6 7 8 UP9301p/s gnd phase boot refin fb vcc ugate gnd lgate 12 3 45 6 7 8 UP9301q/r/t/u gnd phase boot fb vcc ugate gnd lgate 12 3 45 6 7 8 UP9301v/w refin UP9301p/s boot ugate ocs lgate phase refin fb vcc enable disable reference input v in v out option UP9301q/r/t/u/v/w boot ugate gnd lgate phase refin fb vcc enable disable reference input v in v out option
UP9301 3 UP9301-ds-f0001, may 2015 www.upi-semi.com functional pin description .o ne man ni pn oitcnufnip 1t oob ylppuspartstoob croticapacpartstoobehttcennoc.revirdetagreppugnitao lfehtrof toob r oticapacpartstoobeht.tiucricpartstooba mrofotnip esahp ehtdnaniptoobneewteb rofseulavlacipyt.tefsomreppuehtnonrutotegrahcehtsed ivor pc toob o tfu1.0 morfegnar ctahterusne.fu74.0 toob .ciehtraendecalpsi 2e tagu .tuptuorevirdetagreppu derotinomsinipsiht.tefsomreppufoetagehtotnipsihttce nnoc s ahtefsomreppuehtnehw enimretedotyrtiucricnoitcetorphguorht-toohsevitpada ehtyb .ffodenrut 3 dng .ciehtrofdnuorgrewopdnalangis . nipsihtottcepserhtiwderusaem eraslevelsegatlovlla .elbaliavanoitcennocecnadepmitsewolehthguorhtenalp/ dnalsidnuorgehtotnipsihteit sco .gnittesnoitcetorptnerrucrevo .l evelpcoehttesotdngotnipsihtmorfrotsiseratcennoc 4e tagl .tuptuorevirdetagrewol derotinomsinipsiht.tefsomrewolfoetagehtotnipsihttce nnoc n rutsahtefsomrewolehtnehwenimretedotyrtiucricnoitcet orphguorht-toohsevitpadaehtyb .ffo 5c cv .egatlovylppus eht.revirdetagrewolehtdna1039puehtrofylppussaibehts edivorpnipsiht d elpuoced-llewatcennoc.tiucriclortnoclanretnirofddv4 otdetalugeryllanretnisiegatlovylppus e htraendecalpsiroticapacgnilpuocedatahterusne.nipsih totegatlovylppusv2.31otv5.4 .ci 6b f .egatlovkcabdeef morfredividrotsisera.reifilpmarorreehtottupnignitre vniehtsinipsiht .egatlovnoitalugerehttesotdesusidng ottuptuoeht 7n ifer .noitarepo edom gnikcartroftupniecnereferlanretxe h tiw egatlovaseviecernipsiht .r eifilpmarorreehtfotupnignitrevni-nonehttaegatlovecn ereferehtsav0.3otv55.0morfegnar eht,potsotrotallicsoehtsesuacdnarellortnocehtselbas id v3.0nahtrewolnipsihtgnillup .esuecnereferv6.0lanretnirofneponipsihttel.woldlehe botstuptuoetagldnaetagu 8e sahp .edonhctiwsesahp ehtfoniardehtdnatefsomreppuehtfoecruosehtotnipsihtt cennoc pordegatlovehtrotinom otdna,revirdetaguehtrofknisehtsadesusinipsiht.tefso mrewol e vitpadaehtybderotinom oslasinipsiht.noitcetorptnerrucrevoroftefsomrewoleh tssorca y kttohcsa.ffodenrutsahtefsomreppuehtnehwenimretedoty rtiucricnoitcetorphguorht-toohs h cihwegatlovtneisnartevitagenecuderotdednem mocersidnuorgdnanipsihtneewtebedoid .metsysylppusrewopaninom mocsi dapdesopxe .egakcap8-posprof t aehevitcefferofbcp otderedlosllew ebdluohsdapdesopxeeht .dnuorgehtdapdesopxeehttcennoc.noitcudnoc
UP9301 4 UP9301-ds-f0001, may 2015 www.upi-semi.com functional block diagram enable 0.3v pwm vcc amplifier error 0.6v vcc gnd lgate phase ugate boot fb refin v ocp 4vdd reference selection oscillator soft start por gate control logic internal regulator ocp comparator v ref ss (for UP9301p) ocs
UP9301 5 UP9301-ds-f0001, may 2015 www.upi-semi.com functional description the UP9301 is a compact synchronous-rectified buck controller specifically designed to operate from 5v or 12v supply voltage and to deliver high quality output voltage as low as 0.55v. the UP9301 operates at fixed 200/300khz frequency and provides an optimal level of integration to reduce size and cost of the power supply. the UP9301 supports both tracking mode and stand-alone mode operation. the output voltage is tightly regulated to the external reference voltage from 0.55v to 3.0v at tracking mode or to internal 0.6v reference at stand-alone mode. supply voltage the vcc pin receives a well-decoupled 4.5v to 13.2v supply voltage to power the UP9301 control circuit, the lower gate driver and the bootstrap circuit for the higher gate driver. a minimum 0.1uf ceramic capacitor is recommended to bypass the supply voltage. place the bypassing capacitor physically near the ic. an internal linear regulator regulates supply voltage into a 4v voltage 4vdd for internal control logic circuit. no external bypass capacitor is required for filtering the 4vdd voltage. the UP9301 integrates mosfet gate drives that are powered from the vcc pin and support 12v+12v driving capability. a bootstrap diode is embedded to facilitates pcb design and reduce the total bom cost. no external schottky diode is required. converters that consist of UP9301 feature high efficiency without special consideration on the selection of mosfets. note: the embedded bootstrap diode is not a schottky diode having a 0.7v forward voltage. external schottky diode is highly recommended if the vcc voltage is expected to be lower than 5.0v. otherwise the bootstrap diode may be too low for the device to work normally. power on reset and chip enable a power on reset (por) circuitry continuously monitors the supply voltage at vcc pin. once the rising por threshold is exceeded, the UP9301 sets itself to active state and is ready to accept chip enable command. the rising por threshold is typically 4.2v at vcc rising. the refin is a multifunctional pin: external reference input and chip enable as shown in figure 1. to select internal 0.6v reference voltage , just let the refin open. a 30ua current source tries to pull high the refin voltage afterpor that is monitored by the enable comparator monitors for chip enable. a signal level transistor is adequate to pull this pin down to ground and shut down the UP9301. as q1 is turned off, the refin voltage is pulled high to 3.3vdd by the 30ua current source. as the refin voltage acrosses 0.3v threshold level, the enable comparator initiates the operation of the UP9301. the refin voltageis compared with 3.0v voltage to select the reference voltage with 1ms time delay after chip enabling. the internal 0.6v reference voltage is selected as the refin pulled high to internal 3.3vdd. the softstart cycle is initiated after reference selection is completed. to select external reference voltage, connect refin to a voltage source range from 0.55v to 3v. as q1 is turn off, the refin voltage is aligned to the external reference input. as the refin voltage acrosses 0.3v threshold level, the enable comparator initiates the operation of the UP9301. the refin voltage is compared with 3.0v voltage to select the reference voltage with 1ms time delay after chip enabling. the external reference input is selected as the refin voltage is lower than 3.0v. the 30ua current source is turn off if the external reference input is select to eliminate the load effect on the reference input. the softstart cycle is initiated after reference selection is completed. note that the 30ua current source will induces load effect on the external reference input and causes the refin voltage slightly higher than the external reference input during the reference selection. make sure that the external reference input is strong enough so that refin voltage will not be higher than 3.0v. chip enable 0.3v v ref (0.6v) refin reference selection 4vdd 1ms delay reference voltage enable disable reference input 30ua 3.0v q1 figure 1. chip enable and reference selection function softstarta built-in soft start is used to prevent surge current from power supply input during turn on (referring to the functional block diagram). the error amplifier is a three-input device.
UP9301 6 UP9301-ds-f0001, may 2015 www.upi-semi.com functional description reference voltage v ref or the internal soft start voltage ss whichever is smaller dominates the behavior of the non- inverting input of the error amplifier. ss internally ramps up to 4vdd in 50ms after the softstart cycle is intiated. the ramp is created digitally, so there will be 100 small discrete steps. accordingly, the output voltage will follow the ss signal and ramp up smoothly to its target level. the ss signal keeps ramping up after it execeeds the internal reference v ref . however, the reference voltage v ref takes over the behavior of error amplifier after ss > v ref . when the ss signal climb to its ceiling voltage (5v), the UP9301 claims the end of softstart cyclce and enable the under voltage protection of the output voltage. for internal reference voltage, the effective ramp-up time of the output voltage is about 3.6ms. for external reference voltage, the effective ramp up time output voltage is calculated as: re f ss v 6 t = (ms) figure 2 shows a typical start up interval where the refin pin has been released from a grounded (system shutdown) state. v in (5v/div) v out (0.5v/div) lgate (10v/div) i l (5a/div) time : 1ms/div figure 2. softstart behavior. power input detectionthe UP9301 detects phase voltage for the present of power input when the ugate turns on the first time. if the phase voltage does not exceed 2.0v when the ugate turns on, the UP9301 asserts that power input in not ready and stops the softstart cycle. however, the internal ss continues ramping up to 4vdd. another softstart is initiated after ss ramps up to 4vdd. the hiccup period is about 20ms. figure 3 shows the start up interval where v in does not present initially. switching frequency the switching frequency is fixed and can not be changed externally. typical switching frequency is 200/300khz. higher switching frequncy allows higher control bandwidth and faster transient response. however higher swithcing frequency results in higher power loss in both controller and power mosfets. v in (5v/div) v out (0.5v/div) lgate (10v/div) time : 4ms/div figure 3. softstart where vin does not present initially. over current protection (ocp) the UP9301 detects voltage drop across the lower mosfet (v phase ) for overcurrent protection when it is turned on. if v phase is lower than the user-programmable voltage v ocp , the UP9301 asserts ocp and shuts down the converter. the ocp level can be programmed by ocs pin(UP9301p/ s) or fixed at 150mv(UP9301v), 225mv(UP9301r/u/w) and 375mv(UP9301q/t). the UP9301p sources a 20ua current source out of ocs pin. connect resistor r ocs at ocs pin to create voltage level v ocs for ocp setting. the maximum of v ocp should not be larger than 375mv. ocs ocs r ua 20 v = (for UP9301p/s) 4 v v ocs ocp = (for UP9301p/s) ) on ( ds ocp ocp r v i = (a) for example: if v ocp = 375mv, and r ds(on) = 10m , the i ocp will be 37.5a. if v ocp = 225mv, and r ds(on) = 10m , the i ocp will be 22.5a.
UP9301 7 UP9301-ds-f0001, may 2015 www.upi-semi.com under voltage protection (uvp) the fb voltage is monitored for undervoltage protection. the uvp threshold level is typical 0.4v for both stand- alone and tracking mode. when fb voltage is lower than the uvp level, the UP9301 triggers under voltage protection and turn-off all high-side and low-side mosfets. the device will enters hiccup mode until the under-voltage phenomenon is released. functional description
UP9301 8 UP9301-ds-f0001, may 2015 www.upi-semi.com note 1. stresses listed as the above absolute maximum ratings may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. devices are esd sensitive. handling precaution recommended. note 3. ja is measured in the natural convection at t a = 25 o c on a low effective thermal conductivity test board of jedec 51-3 thermal measurement standard. note 4. the device is not guaranteed to function outside its operating conditions. package thermal resistance (note 3) psop-8l ja --------------------------------------------------------------------------------------------------------------------- 50 c/w psop-8l jc ---------------------------------------------------------------------------------------------------------------------- 5 c/w sop-8l ja --------------------------------------------------------------------------------------------------------------------- 160 c/w sop-8l jc ---------------------------------------------------------------------------------------------------------------------- 39 c/w power dissipation, p d @ t a = 25 c psop-8l ---------------------------------------------------------------------------------------------------------------------------------- 2w sop-8l ---------------------------------------------------------------------------------------------------------------------------------- 0.63w (note 4) operating junction temperature range --------------------------------------------------------------------- -40 c to +125 c operating ambient temperature ra nge ---------------------------------------------------------------------------------- -40 c to +85 c supply input voltage, v cc ----------------------------------------------------------------------------------------------------- +4.5v to 13.2v absolute maximum rating thermal information recommended operation conditions (note 1) supply input voltage, vcc ------------------------------------------------------------------------------------------------- -0.3v to +15v phase to gnd dc ---------------------------------------------------------------------------------------------------------------------------- -5v to 15v < 200ns ------------------------------------------------------------------------------------------------------------------- -10v to 30v boot to gnd dc -------------------------------------------------------------------------------------------------------------- -0.3v to phase +15v < 200ns ----------------------------------------------------------------------------------------------------------------- -0.3v to 42v lgate to gnd dc ---------------------------------------------------------------------------------------------------------------------------- -1v to 15v < 200ns --------------------------------------------------------------------------------------------------------------------- -5v to 30v ugate to phase dc ------------------------------------------------------------------------------------------------------------------------- -0.3v to 15v < 200ns --------------------------------------------------------------------------------------------------------------------- -2v to 20v input, output or i/o voltage -------------------------------------------------------------------------------------------------- -0.3v to +6v storage temperature range ----------------------------------------------------------------------------------------------- -65 o c to +150 o c junction temperature --------------------------------------------------------------------------------------------------------------------- 150 o c lead temperature (soldering, 10 sec) ------------------------------------------------------------------------------------------------ 260 o c esd rating (note 2) hbm (human body mode) -------------------------------------------------------------------------------------------------------- 2kv mm (machine mode) ---------------------------------------------------------------------------------------------------------------- 200v
UP9301 9 UP9301-ds-f0001, may 2015 www.upi-semi.com retemara pl obmy ss noitidnoctse tn i mp y tx am s tinu tupniylppus egatlovylppu sv cc 5. 4- -2 .3 1v tnerrucylppu si cc v;nepo etagl,etagu cc gnihctiws,v21 =- -4- -a m tnerrucylppustnecseiu qi q_cc v bf gnihctiwson,v7.0 =- -4- -a m egatlovtupnirewo pv ni 0. 3- -2 .3 1v teser norewop dlohserhtro pv htrcc v cc gnisi r0 . 42 . 44 . 4v siseretsyh ro pv syhcc - -3 . 0- -v rotallicso ycneuqerfgninnureer ff cso r/q/p1039p u0 7 10 0 20 3 2z hk w/v/u/t/s1039p u5 5 20 0 35 4 3z hk edutilpmapmar ? v cso v cc v21 =- -8 . 1- -v p-p reifilpmarorre niag cdpoolnep oo an gisedybdeetnarau g5 50 7- -b d tcudorphtdiwdnab-nia gw b gn gisedybdeetnarau g- -0 1- -z hm etar wel sr sn gisedybdeetnarau g3 6 - -s u/v ecnatcudnocsnar tn gisedybdeetnarau g- -- -7 . 0s m srevirdetagrellortnoc m w p tnerrucgnicruosetagrepp ui crs_gu v toob v- esahp v,v21= toob v- etagu v6 =- -1 -- -a tnerrucgniknisetagrepp ui kns_gu v toob v- esahp v,v21= etagu v- esahp v6 =- -5 . 1- -a retagreppu )no(sd gnikni sr kns_gu v etagu v- esahp v1.0 =- -24 tnerrucgnicruosetagrewo li crs_gl v cc v- etagl v6 =- -1 -- -a tnerrucgniknisetagrewo li kns_gl v etagl v6 =- -2- -a retagrewol )no(sd gnikni sr kns_gl v etagl v1.0 =- -24 etaglotgnillafesahp yaledgnisir v cc v;v21= esahp votv2.1< etagl v2.1 >- -0 30 9s n etaguotgnillafetagl yaledgnisir v cc ;v21= v etagl v(otv2.1< etagu v- esahp v2.1>) - -0 30 9s n (v cc = 12v, t a = 25 o c, unless otherwise specified) electrical characteristics
UP9301 10 UP9301-ds-f0001, may 2015 www.upi-semi.com retemara pl obmy ss noitidnoctse tn i mp y tx am s tinu egatlovecnerefer egatlovkcabdeeflanimo nv bf edom enoladnat s1 95. 00 06. 09 06. 0v ycaruccaegatlovtuptuo v| bf v- nifer v,| nifer ,v0.1~v55.0= edom gnikcart - -- -5 1v m v| bf v- nifer v/| nifer v, nifer ,v0.3~v0.1= edom gnikcart - -- -5 . 1% dlohserhtelbane nife rv nifer - -3 . 05 3. 0v egatlovecnereferlanretx ev nifer 55. 0- -0 . 3v noitcetorp noitcetorpegatlovredn uv pvu_bf 3. 04 . 05 . 0v dlohserhttnerrucrev ov esahp t/q1039p u- -5 73 -- - vm w/u/r1039p u- -5 22 -- - v1039p u- -0 51 -- - egnarelbam margorp pc ov pco s/p1039p u5 73 -- -0 01 -v m pcoroftnerrucecruos sco gnittes i sco - -0 2- -a u lavretnitrats-tfo st ss edom enoladnat s4 . 26 . 38 . 4s m electrical characteristics
UP9301 11 UP9301-ds-f0001, may 2015 www.upi-semi.com lgate (10v/div) refin (0.5v/div) v out (0.5v/div) ugate (5v/div) lgate (5v/div) phase (5v/div) ugate-phase (5v/div) ugate (5v/div) lgate (5v/div) phase (5v/div) ugate-phase (5v/div) refin (2v/div) v out (0.5v/div) lgate (10v/div) i l (10a/div) refin (2v/div) v out (0.5v/div) lgate (10v/div) i l (5a/div) v in (5v/div) v out (0.5v/div) lgate (10v/div) i l (5a/div) typical operation characteristics switching waveforms: ugate trun off time : 40ns/div v in = 12v, i out = 10a refin operation time : 10ms/div v in = 12v, c out = 2000uf, i out = 6a power on waveforms time : 1ms/div v in =12v, v out = 1.2v, c out = 2000uf, no load turn on from refin time : 2ms/div v in =12v, v out = 1.2v, c out = 2000uf, no load turn off from refin time : 10us/div v in = 12v, v out = 1.2v, c out = 2000uf, i out = 6a switching waveforms: ugate turn on time : 40ns/div v in = 12v, i out = 10a
UP9301 12 UP9301-ds-f0001, may 2015 www.upi-semi.com -3.0 -2.0 -1.0 0.0 1.0 2.0 3.0 0 5 10 15 20 25 30 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 4 6 8 10 12 14 v out (0.5v/div) phase (5v/div) i l (50a/div) v out (0.5v/div) phase (5v/div) i l (50a/div) v out(ac) (100mv/div) phase (10v/div) i out (10a/div) lgate (10v/div) v in (5v/div) v out (0.5v/div) typical operation characteristics power sequencing operation time : 1ms/div v cc =12v ready, v out = 1.2v, c out = 2000uf, no load load transient response time : 10us/div v in =12v, v out = 1.2v, c out = 2000uf over current protection time : 40us/div v in = 12v, v out = 1.2v, c out = 2000uf, power on ! short v out to ground over current protection time : 400us/div v in = 12v, v out = 1.2v, c out = 2000uf, short v out ! power on load regulation output current (a) output voltage deviation (%) line regulation input voltage (v) output voltage deviation (%)
UP9301 13 UP9301-ds-f0001, may 2015 www.upi-semi.com 285 290 295 300 305 310 315 4681 01 21 4 -3.0 -2.0 -1.0 0.0 1.0 2.0 3.0 -50 -25 0 25 50 75 100 125 255 265 275 285 295 305 315 325 335 -50 -25 0 25 50 75 100 125 typical operation characteristics switching frequency vs. input voltage input voltage (v) switching frequency (khz) output voltage vs. junction temperature junction temperature ( o c) output voltage varition (%) switching frequency vs. junction temperature junction temperature ( o c) switching frequency (khz)
UP9301 14 UP9301-ds-f0001, may 2015 www.upi-semi.com power mosfet selectionexternal component selection is primarily determined by the maximum load current and begins with the selection of power mosfet switches. the UP9301 requires two external n-channel power mosfets for upper (controlled) and lower (synchronous) switches. important parameters for the power mosfets are the breakdown voltage v (br)dss , on-resistance r ds(on) , reverse transfer capacitance c rss , maximum current i ds(max) , gate supply requirements, and thermal management requirements. the gate drive voltage is powered by vcc pin that receives 4.5v~13.2v supply voltage. when operating with a 12v power supply for vcc (or down to a minimum supply voltage of 8v), a wide variety of nmosfets can be used. logic-level threshold mosfet should be used if the input voltage is expected to drop below 8v. since the lower mosfet is used as the current sensing element, particular attention must be paid to its on-resistance. look for r ds(on) ratings at lowest gate driving voltage.special cautions should be exercised on the lower switch exhibiting very low threshold voltage v gs(th) . the shoot- through protection present aboard the UP9301 may be circumvented by these mosfets if they have large parasitic impedences and/or capacitances that would inhibit the gate of the mosfet from being discharged below its threshold level before the complementary mosfet is turned on. also avoid mosfets with excessive switching times; the circuitry is expecting transitions to occur in under 50 nsec or so. in high-current applications, the mosfet power dissipation, package selection and heatsink are the dominant design factors. the power dissipation includes two loss components; conduction loss and switching loss. the conduction losses are the largest component of power dissipation for both the upper and the lower mosfets. these losses are distributed between the two mosfets according to duty cycle. since the UP9301 is operating in continuous conduction mode, the duty cycles for the mosfets are: in out up v v d = ; in out in lo v v v d ? = the resulting power dissipation in the mosfets at maximum output current are: os c sw in out up ) on ( ds 2 out up f t v i5.0 d r i p + = l o ) on ( ds 2 out lo d r i p = where t sw is the combined switch on and off time. application information both mosfets have i 2 r losses and the top mosfet includes an additional term for switching losses, which are largest at high input voltages. the bottom mosfet losses are greatest when the bottom duty cycle is near 100%, during a short-circuit or at high input voltage. these equations assume linear voltage current transitions and do not adequately model power loss due the reverse-recovery of the lower mosfets body diode. ensure that both mosfets are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. a separate heatsink may be necessary depending upon mosfet power, package type, ambient temperature and air flow. the gate-charge losses are dissipated by the UP9301 and dont heat the mosfets. however, large gate charge increases the switching interval, t sw that increases the mosfet switching losses. the gate-charge losses are calculated as: os c rss in lo _ iss up _ iss cc cc g f) c v ) c c( v( v p + + = where c iss_up is the input capacitance of the upper mosfet, c iss_lo is the input capacitance of the lower mosfet, and c rss_up is the reverse transfer capacitance of the upper mosfet. make sure that the gate-charge loss will not cause over temperature at UP9301, especially with large gate capacitance and high supply voltage. output inductor selection output inductor selection usually is based the considerations of inductance, rated current, size requirement, and dc resistance (dc) given the desired input and output voltages, the inductor value and operating frequency determine the ripple current: ) v v 1( v l f 1 i in out out out osc l ? = ? lower ripple current reduces core losses in the inductor, esr losses in the output capacitors and output voltage ripple. highest efficiency operation is obtained at low frequency with small ripple current. however, achieving this requires a large inductor. there is a tradeoff between component size, efficiency and operating frequency. a reasonable starting point is to choose a ripple current that is about 40% of i out(max) . there is another tradeoff between output ripple current/ voltage and response time to a transient load. increasing the value of inductance reduces the output ripple current and voltage. however, the large inductance values reduce the converters response time to a load transient.
UP9301 15 UP9301-ds-f0001, may 2015 www.upi-semi.com maximum current ratings of the inductor are generally specified in two methods: permissible dc current and saturation current. permissible dc current is the allowable dc current that causes 40 o c temperature raise. the saturation current is the allowable current that causes 10% inductance loss. make sure that the inductor will not saturate over the operation conditions including temperature range, input voltage range, and maximum output current. the size requirements refer to the area and height requirement for a particular design. for better efficiency, choose a low dc resistance inductor. dcr is usually inversely proportional to size. different core materials and shapes will change the size/ current and price/current relationship of an inductor. toroid or shielded pot cores in ferrite or permalloy materials are small and dont radi ate much energy, but generally cost more than powdered iron core inductors with similar electrical characteristics. the choice of which style inductor to use often depends more on the price vs. size requirements and any radiated field/emi requirements. input capacitor selection the synchronous-rectified buck converter draws pulsed current with sharp edges from the input capacitor resulting in ripples and spikes at the input supply voltage. use a mix of input bypass capacitors to control the voltage overshoot across the mosfets. use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time upper mosfet turns on. place the small ceramic capacitors physically close to the mosfets and between the drain of upper moset and the source of lower mosfet to avoid the stray inductance along the connection trace. the important parameters for the bulk input capacitor are the voltage rating and the rms current rating. for reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest rms current required by the circuit. the capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. the rms current rating requirement for the input capacitor of a buck converter is calculated as: in out in out ) max ( out ) rms ( in v ) v v( v i i ? = this formula has a maximum at v in = 2v out , where i in(rms) = i out(rms) /2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. note that the capacitor manufa cturers ri pple current ratings are often based on 2000 hours of life. this makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. always consult the manufacturer if there is any question. for a through-hole design, several electrolytic capacitors may be needed. for surface mount designs, solid tantalum capacitors can also be used, but caution must be exercised with regard to the capacitor surge current rating. these capacitors must be capable of handling the surge-current at power-up. some capacitor series available from reputable manufacturers are surge current tested. output capacitor selection an output capacitor is required to filter the output and supply the load transient current. the selection of c out is primarily determined by the esr required to minimize voltage ripple and load step transients. the output ripple ? v out is approximately bounded by: ) c f8 1 esr (i v out osc l out + ? ? since ? il increases with input voltage, the output ripple is highest at maximum input voltage. typically, once the esr requirement is satisfied, the capacitance is adequate for filtering and has the necessary rms current rating. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. special polymer capacitors offer very low esr but have lower capacitance density than other types. the load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. these requirements are generally met with a mix of capacitors and careful layout. modern components and loads are capable of producing transient load rates above 1a/ns. high frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. the bulk filter capacitor values are generally determined by the esr (effective series resistance) and voltage rating requirements rather than actual capacitance requirements. high frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. consult with the manufacturer of the load on specific decoupling requirements. application information
UP9301 16 UP9301-ds-f0001, may 2015 www.upi-semi.com use only specialized low-esr capacitors intended for switching-regulator applications for the bulk capacitors. the bulk capacitors esr will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. an aluminum electrolytic capa citors esr value is related to the case size with lower esr available in larger case sizes. however, the equivalent series inductance (esl) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. unfortunately, esl is not a specified parameter. work with your capacitor supplier and measure the capa citors impedance with frequency to select a suitable component. in most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. bootstrap capacitor selection an external bootstrap capacitor c boot connected to the boot pin supplies the gate drive voltage for the upper mosfet. this capacitor is charged through the internal diode when the phase node is low. when the upper mosfet turns on, the phase node rises to v in and the boot pin rises to approximately v in + v cc . the boot capacitor needs to store about 100 times the gate charge required by the upper mosfet. in most applications 0.1uf to 0.47uf, x5r or x7r dielectric capacitor is adequate. pcb layout considerations high speed switching and relatively large peak currents in a synchronous-rectified buck converter make the pcb layout a very important part of design. fast current switching from one device to another in a synchronous-rectified buck converter causes voltage spikes across the interconnecting impedances and parasitic circuit elements. the voltage spikes can degrade efficiency and radiate noise that result in overvoltage stress on devices. careful component placement layout and printed circuit design minimizes the voltage spikes induced in the converter. follow the layout guidelines for optimal performance of UP9301. 1 the upper and lower mosfets turn on/off and conduct pulsed current alternatively with high slew rate transition. any inductance in the switched current path generates a large voltage spike during the switching. the interconnecting wires indicated by red heavy lines conduct pulsed current with sharp transient and should be part of a ground or power plane in a printed circuit board to minimize the voltage spike. make all the connection the top layer with wide, copper filled areas. 2 place the power components as physically close as possible. 2.1 place the input capacitors, especially the high- frequency ceramic decoupling capacitors, directly to the drain of upper mosfet ad the source of the lower mosfet. to reduce the esr replace the single input capacitor with two parallel units 2.2 place the output capacitor between the converter and load. 3 place the UP9301 near the upper and lower mosfets with pins 1 to 4 facing the power components. keep the components connected to pins 4 to 8 close to the UP9301 and away from the inductor and other noise sources (noise sensitive components). 4 use a dedicated grounding plane and use vias to ground all critical components to this layer. the ground plane layer should not have any traces and it should be as close as possible to the layer with power mosfets. use an immediate via to connect the components to ground plane including gnd of UP9301. use several bigger vias for power components. 5 apply another solid layer as a power plane and cut this plane into smaller islands of common voltage levels. the power plane should support the input power and output power nodes to maintain good voltage filtering and to keep power losses low. also, for higher currents, it is recommended to use a multilayer board to help with heat sinking power components. 6 the phase node is subject to very high dv/dt voltages. stray capacitance between this island and the surrounding circuitry tend to induce current spike and capacitive noise coupling. keep the sensitive circuit away from the phase node and keep the pcb areasmall to limit the capacitive coupling. however, the pcb area should be kept moderate since it also acts as main heat convection path of the lower mosfet. 7 UP9301 sources/sinks impulse current with 2a peak to turn on/off the upper and lower mosfets. the connecting trance between the controller and gate/ source of the mosfet should be wide and short to minimize the parasitic inductance along the traces. 8 flood all unused areas on all layers with copper. flooding with copper will reduce the temperature riseof power component. 9 provide local vcc decoupling between vcc and gnd pins. locate the capacitor, c boot as close as practical to the boot and phase pins. application information
UP9301 17 UP9301-ds-f0001, may 2015 www.upi-semi.com package information psop - 8l note 1.package outline unit description: bsc: basic. represents theoretical exact dimension or dimension target min: minimum dimension specified. max: maximum dimension specified. ref: reference. represents dimension for reference use only. this value is not a device specification. typ. typical. provided as a general value. this value is not a device specification. 2.dimensions in millimeters. 3.drawing not to scale. 4.these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.15mm. 0.31 - 0.51 4.80 - 5.00 5.79 - 6.20 0.10 - 0.25 0.40 - 1.27 1.27 bsc 3.80 - 4.00 1.80 - 2.40 1.80 - 2.40 0.00 - 0.15 1.7 max
UP9301 18 UP9301-ds-f0001, may 2015 www.upi-semi.com package information sop - 8l note 1.package outline unit description: bsc: basic. represents theoretical exact dimension or dimension target min: minimum dimension specified. max: maximum dimension specified. ref: reference. represents dimension for reference use only. this value is not a device specification. typ. typical. provided as a general value. this value is not a device specification. 2.dimensions in millimeters. 3.drawing not to scale. 4.these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.15mm. 0.31 - 0.51 4.80 - 5.00 5.80 - 6.20 0.10 - 0.25 0.10 - 0.25 0.40 - 1.27 1.27 bsc 3.80 - 4.00 1.75 max
UP9301 19 UP9301-ds-f0001, may 2015 www.upi-semi.com important notice upi and its subsidiaries reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. upi products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment. however, no res ponsibility is assumed by upi or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of upi or its subsidiaries. copyright ( c ) 2014, upi semiconductor corp. upi semiconductor corp. headquarter 9f.,no.5, taiyuan 1st st. zhubei city, hsinchu taiwan, r.o.c. tel : 886.3.560.1666 fax : 886.3.560.1888 upi semiconductor corp. sales branch office 12f-5, no. 408, ruiguang rd. neihu district, taipei taiwan, r.o.c. tel : 886.2.8751.2062 fax : 886.2.8751.5064

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